AMD GCN3 ISA Architecture Manual

Infrastructure

AMD GCN ISA  Architecture document describes the environment, organization, and program state of AMD GCN Generation 3 devices which includes Radeon R9 family of devices.  It details the instruction set and the microcode formats native to this family of processors that are accessible to programmers and compilers.

Audience

This document is intended for programmers writing application and system software, including operating systems, compilers, loaders, linkers, device drivers, and system utilities. It assumes that programmers are writing compute-intensive parallel applications (streaming applications) and assumes an understanding of requisite programming practices.

Organization

  • Chapter 1 overview of the AMD GCN processors’ hardware and programming environment.
  • Chapter 2 describes the organization of GCN programs.
  • Chapter 3 describes the program state that is maintained.
  • Chapter 4 describes the program flow.
  • Chapter 5 describes the scalar ALU operations.
  • Chapter 6 describes the vector ALU operations.
  • Chapter 7 describes the scalar memory operations.
  • Chapter 8 describes the vector memory operations.
  • Chapter 9 provides information about the flat memory instructions.
  • Chapter 10 describes the data share operations.
  • Chapter 11 describes exporting the parameters of pixel color and vertex shaders.
  • Chapter 12 describes instruction details, first by the microcode format to which they belong, then in alphabetic order.
  • Chapter 13 provides a detailed specification of each microcode format.

Download the manual here.

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