AMD GPU architecture programming documentation
A repository of AMD Instruction Set Architecture (ISA) and Micro Engine Scheduler (MES) firmware documentation
A repository of AMD Instruction Set Architecture (ISA) and Micro Engine Scheduler (MES) firmware documentation
This presentation introduces a novel algorithm for PC and console developers to efficiently generate sparse distance fields in real-time.
Our one-stop resource for getting great AMD RDNA™ performance on Vulkan® and DirectX®12 APIs!
This talk introduces compute shaders, explaining ideas from a software and hardware perspective, as well as considerations when writing compute shaders.
This presentation by one of our engineers at GIC 2020 provides an introduction to the graphics pipeline.
This video will take you from the original source code down to the RDNA ISA. It covers control-flow, bindless resource access and scalarization, along with DXC, instruction selection, scheduling, and register allocation for the RDNA instruction set.
Learn about the details of RDNA and how it differs from the previous GCN architecture. Includes examples of optimizations based on the case study of implementing an efficient downsampler. Covers topics such as characteristics of workload distribution, shader optimizations, and efficient texture access.
With RDNA, AMD has revisited almost every block in the hardware with a drive, tenacity and focus to make RDNA our best ever architecture for graphics and low latency compute.
The Game Engineering team – in collaboration with others – has put together an RDNA architecture presentation containing doodles, notes and explanation about the structure of RDNA, how it works, and the differences from our previous architectures.
The RDNA Shader Instruction Set Architecture reference guide is now available.