AMD GPU architecture programming documentation

If you’re looking to work at a lower level with AMD hardware, this page contains links to some of our publicly available PDFs.

You may also be interested in our machine-readable AMD GPU ISA specifications.

AMD MES firmware

Micro engine scheduler (MES) firmware is responsible for the scheduling of the graphics and compute work on the AMD RDNA™ 3 GPUs.

This document provides an overview of the AMD RDNA 3 scheduling architecture by describing the key scheduler firmware (MES) and hardware (Queue Manager) components that participate in the scheduling.

This document is intended to introduce the reader to the overall scheduling architecture and is not meant to serve as a programming guide.

Get the AMD RDNA™ 3 MES firmware document

AMD GPU ISAs

Understanding the instruction-level capabilities of any processor is a worthwhile endeavour for any developer writing code for it, even if the instructions that get executed are almost always hidden behind a higher-level language and compiler. If you’re working at that level as most are, the extra understanding you get from knowing exactly how the machine executes will hopefully help you write better code for it.

We’ve been releasing the Instruction Set Architecture (ISA) manuals for our GPUs for a long time now, and they reach all the way back to the venerable Radeon R600 (a GPU which helped usher in the DirectX®10 era back in 2006!)

The main purposes of an ISA are to:

Specify the language constructs and behavior, including the organization of each type of instruction in both text syntax and binary format.
Provide a reference of instruction operation that compiler writers can use to maximize performance of the processor.

These ISAs are intended for programmers writing application and system software, including operating systems, compilers, loaders, linkers, device drivers, and system utilities. It assumes that programmers are writing compute-intensive parallel applications (streaming applications) and assumes an understanding of requisite programming practices.

AMD GPU machine-readable ISA specifications

We provide machine-readable ISA specifications for our AMD RDNA and AMD CDNA architectures. We’ve also written a C++ IsaDecoder API and shared example code to make it even easier to get started.

AMD machine-readable GPU ISA documentation

AMD's machine-readable GPU ISA specifications are a set of XML files that describe AMD’s latest GPU Instruction Set Architectures (ISAs)

Decoding instructions with the machine-readable AMD GPU ISA specifications

A simple C++ program demonstrating how easy it is to decode instructions using the IsaDecoder API.

AMD Radeon™ GPU Analyzer (RGA)

RGA is an offline shader compiler that can show the ISA of a compiled shader. RGA is part of the Radeon Developer Tool Suite (RDTS).

Find out more about RGA:

AMD Radeon™ GPU Analyzer

Radeon GPU Analyzer is an offline compiler and performance analysis tool for DirectX®, Vulkan®, SPIR-V™, OpenGL® and OpenCL™.

Looking for more?

Tech Docs @ AMD.com

Not finding what you need here, or looking for something a bit more niche or historical? You may find what you’re after with AMD’s Technical Documentation.